ArcLang documentation

ArcLang is a textual modeling language for the Arcadia method and a strict compiler written in Rust. A system model is a set of plain text files: it is versioned in Git, reviewed in pull requests, checked in continuous integration, and compiled to diagrams and exchange formats.

This documentation describes version 4.12.0. Each ArcLang sample is compiled and each command is run when the site is built, so what you read is what the released compiler does.

What's new in 4.6

ArcLang 4.6 puts the model through the same pipeline as code, from physics to release. These pages describe it; each says what the 4.5.0 binaries do not have, because the site documents the next release before it is published.

• Semantic git: arclang diff --from/--to, the history of one element, a merge driver that merges by element identity, and baselines an auditor can verify. In VS Code: compare mode, element history and a conflicts view.
• CI/CD: arclang ci init writes the pipeline for GitHub Actions, GitLab CI, Azure DevOps or Jenkins; ci run, a SARIF 2.1.0 log for code scanning, and a pull-request report that says what the change does to the gate. The generated pipelines are not run against the providers by us.
• Simulation: ports that carry physics become Modelica connectors, a test case simulates in OpenModelica, the verdict reaches the gate. The export now draws the architecture for Modex and OMEdit, and VS Code guides the setup.
• VS Code: impact analysis, live tables and matrices, import and save as, layers and groups, themes and PowerPoint export, a choice of eight AI providers, and what the browser build can and cannot do.

Learn MBSE

New to model-based systems engineering? These four pages take you from the first idea to a complete model.

• MBSE in 15 minutes: one model instead of documents; needs and solutions, functions and components, levels, traceability and verification.
• Tutorial: your first model: model a home heating system from a blank page in the playground, step by step, up to a passing production gate.
• Modeling with Arcadia: the five levels of the method of the Capella tool, its diagrams and the matching ArcLang blocks and views.
• Modeling with SysML v2: the core concepts of the standard, how each maps to ArcLang, and the tutorial model exported to SysML v2.

Start here

• Getting started: install the compiler, write a first model, make it pass the production gate.
• Language tour: the five Arcadia layers, requirements, traces, the data model, state machines and scenarios.
• Quantities, types and constraints: latency: 25 ms is a duration, and a budget is an assertion the compiler evaluates.

Work with a model

• Diagrams: Arcadia viewpoint diagrams generated from the model, in a viewer that needs no network.
• Production gate: a PASS or FAIL verdict on requirements coverage, hazard analysis and timing budgets, for ISO 26262, DO-178C and IEC 61508.
• Review and change: semantic diff, impact analysis with what-if, formatter and scripted edits.
• Semantic git: diff by revision, element history, merge by element, baselines.
• Simulation: requirements verified by simulating the physical architecture in OpenModelica.
• CI/CD: the gate, SARIF and a pull-request report in your pipeline.
• VS Code: the extension, a model workbench with editable diagrams, tables, impact analysis, git, CI and simulation, an AI agent and SysML v2 files.

From the model to hardware

• Embedded C: state machines and data-flow blocks compiled to neutral C, wired from one machine to the next, one I/O interface, one task per binding with its schedule analysed, software in the loop, the plant in the loop (an FMU from any tool, FMI 2.0 or 3.0), MISRA C 2012.
• Targets and processor in the loop: target packages, a Zephyr application for a LiteX VexRiscv SoC, the generated C run on the simulated core in Renode.
• Embedded FPGA: fixed point derived from the model's ranges, VHDL checked bit for bit against C, synthesis, and HW/SW partitioning on measured numbers.
• Processor and logic: both in one SoC, simulated with Verilator, in the loop with the plant, built to a bitstream.
• Realization ladder: each requirement from simulation to SIL, PIL, HDL, SoC, board and twin, with cached verdicts, and arclang realize to climb.
• The platform: one typed model with deterministic tools behind it, its domains, and what comes next.

Exchange with other tools

• Capella: round-trip with a native Capella model, and how ArcLang compares with Capella.
• SysML v2: textual export validated by the OMG pilot implementation, and how ArcLang compares with SysML v2.
• Exchange formats: ReqIF, Simulink and System Composer, FMI 2.0, Modelica, C headers and Protobuf.
• HTTP API: compile endpoint and the Systems Modeling API, with git history.

Reference

• Command line: every command, with its real options.
• Metamodel: element kinds, typed attributes, enumerations and units, generated from the compiler.
• Grammar: the canonical EBNF.
• Migrating to 4.0 and the versioning policy.

What ArcLang does not do

The project states its limits as plainly as its features. Layout of diagrams is automatic, with optional manual arrangement saved next to the model; there is no free-form drawing. Hazards and FMEA have no SysML v2 construct and are exported as tagged requirements. Some commands exist but answer Not implemented instead of pretending: repl, clean, new, sync, plugin, and the fault-tree and report generation of safety. The README keeps the complete list.